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• W1496308985 abstract "System reliability becomes one of the major design concerns in nanoscale VLSI technologies. To cope with the increasing design complexity and the challenge of cost-efficient reliability improvement, modular and hierarchical optimizations are essential in the design space exploration. In this paper a novel scheduling and binding approach is proposed to investigate the potentials of reliability enhancement in high level synthesis. Inspired by the observation that the timing resource within individual clock cycle can be redistributed to maximize reliability, we propose a reliability-aware operation chaining technique, considering both the behavioral operation vulnerabilities and RTL reliability-cost tradeoffs in functional units. Using a characterized RTL component library regarding soft error, the experimental results show that compared to the traditional chaining, with the same timing constraint the proposed technique can generate the RTL with 3X reduction of the system failure rate, while introducing only 15% area and 16% power overhead." @default.
• W1496308985 created "2016-06-24" @default.
• W1496308985 creator A5042081750 @default.
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• W1496308985 date "2015-05-01" @default.
• W1496308985 modified "2023-09-24" @default.
• W1496308985 title "Reliability-aware operation chaining in high level synthesis" @default.
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• W1496308985 doi "https://doi.org/10.1109/ets.2015.7138739" @default.
• W1496308985 hasPublicationYear "2015" @default.
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