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- W2182709698 abstract "Abstract DL1: Many-Core Chips: The New High-Performance Computing Platform Sacling as we know it is taking a different direction from the last three decades. Chips with tens of billions of transistors and hundreds of cores are expected to be the future of scaling. These chips will achieve performance through parallelism and application specific optimized cores. This trend will use superior technologies to integrate more cores on a chip rather than to push the frequency envelope as in the past. It is expected that every aspect of design and analysis will need to be modified to accommodate this new platform and trend. There is a clear need for new CAD tools and design methodologies that are very different from existing tools in both their focus and scope. This talk will delve into the specific challenges with respect to both design and CAD that is required for these many core chips. The talk will also provide an overview into the market and technology factors guiding and driving this trend. Attendees will be provided with insight into both present and future research vectors to support this nascent exponential. Abstract DL2: Challenges for Electronics Design in the Nano-Scale Semiconductor technologies exhibited explosive growth in complexity and speed over the last two decades. Since the early 1980s, the device sizes have scaled down from few micrometers to tens of Nano-meters and the operating frequencies have increased from a few megahertz to several gigahertz. Also, the spacing between devices and interconnect have dramatically decreased due to the continuous scaling down of the technology feature size. These trends have led to issues and challenges in the design and analysis of high performance integrated circuits that previous generations did not exhibit. Most of these issues are at the circuit and interconnect (physical) levels. Also, these issues are expected only to increase in importance in future generations of integrated circuits. This talk will overview the most important challenges for electronics design in the nano-scale." @default.
- W2182709698 created "2016-06-24" @default.
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- W2182709698 date "2012-01-01" @default.
- W2182709698 modified "2023-09-27" @default.
- W2182709698 title "IEEE CASS/EDS/SSCS Ottawa Joint Chapters, IEEE ComSoc/BTS/CES Ottawa Joint Chapter AP/MTT, CPMT and Computer Society & DoE-Carleton Joint Seminar (CASS Distinguished Lecture) are inviting all interested IEEE members and nonmembers to a seminar on DL1: Title: Many-Core Chips: The New High-Performance Computing Platform DL2: Title: Challenges for Electronics Design in the Nano-Scale" @default.
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