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- W2375248095 abstract "A continuous-rate clock and data recovery circuit was designed in 0.18μm CMOS process.The CDR circuit included mainly a full-rate bang-bang phase frequency detector,multi-band ring voltage-controlled oscillator(VCO),charge pump and other modules.The full-rate phase detector PFD not only had good functions,but also had simple structure,low power consumption and area.Multi-band ring voltage-controlled oscillator not only had a wide tuning range,but also had a low tuning loop gain,which had settled the conflict between high oscillating frequency and low tuning gain.By using the charge pump through bootstrap reference and op amp,various non-ideal factors were reduced.Simulation results showed that the circuit was working properly,the CDR circuit could recover the NRZ data from 622 to 3 125Mb/s.The core size was 265μm ×786μm.At 1.8Vsupply voltage and3 125Mb/s input pseudo-random rate,the power consumption was 100.8mW,the recovered data and clock jitter peak was 5.38 ps and 4.81 ps respectively." @default.
- W2375248095 created "2016-06-24" @default.
- W2375248095 creator A5053037078 @default.
- W2375248095 date "2014-01-01" @default.
- W2375248095 modified "2023-09-26" @default.
- W2375248095 title "Design of a Wide-Range Continuous-Rate Clock and Data Recovery Circuit" @default.
- W2375248095 hasPublicationYear "2014" @default.
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