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- W4244661885 abstract "On-chip interconnection networks simplify the increasingly challenging process of integrating multiple functional modules in modern Systems-on-Chip (SoCs). The routers are the heart and backbone of such networks, and their implementation cost (area/power) determines the cost of the whole network. In this paper, we explore the time-multiplexing of a router's output ports via a folded datapath and control, where only a portion of the router's arbiters and crossbar multiplexers are implemented, as a means to reduce the cost of the router without sacrificing performance. In parallel, we propose the incorporation of the switch-folded routers into a new form of heterogeneous network topologies, comprising both folded (time-multiplexed) and unfolded (conventional) routers, which leads to effectively the same network performance, but at lower area/energy, as compared to topologies composed entirely of full-fledged wormhole or virtual-channel-based router designs." @default.
- W4244661885 created "2022-05-12" @default.
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- W4244661885 date "2013-01-01" @default.
- W4244661885 modified "2023-09-27" @default.
- W4244661885 title "Switch Folding: Network-on-Chip Routers with Time-Multiplexed Output Ports" @default.
- W4244661885 doi "https://doi.org/10.7873/date.2013.081" @default.
- W4244661885 hasPublicationYear "2013" @default.
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