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- W4299907093 abstract "This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation (CLM) and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed." @default.
- W4299907093 created "2022-10-03" @default.
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- W4299907093 date "2010-08-14" @default.
- W4299907093 modified "2023-09-23" @default.
- W4299907093 title "Controlling Short-channel Effects in Deep Submicron SOI MOSFETs for Improved Reliability: A Review" @default.
- W4299907093 doi "https://doi.org/10.48550/arxiv.1008.2427" @default.
- W4299907093 hasPublicationYear "2010" @default.
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