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• W1997495328 abstract "A Sparse Matrix Superchip (SMS), a reconfigurable architecture for VLSI processing arrays is proposed. Two major issues discussed in this paper are reconfiguration to achieve defect/fault tolerance for yield improvement and to customise the chip for different network topologies. The proposed architecture incorporates a sparse crossbar matrix of switches to interconnect two rows of processing elements (PEs) located above and below the matrix. The use of the SMS for matrix-matrix and matrix-vector multiplications for signal processing applications are illustrated. The SMS implementation promise to be twice as fast and more flexible in terms of communication than the nearest neighbour systolic arrays. It also requires less number of processing elements. The SMS channel router with tapering capability could be very useful for routing WSI circuits." @default.
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• W1997495328 date "1991-03-01" @default.
• W1997495328 modified "2023-10-17" @default.
• W1997495328 title "Sparse matrix superchip: A reconfigurable architecture for VLSI processing arrays" @default.
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• W1997495328 doi "https://doi.org/10.1016/0167-9260(91)90005-6" @default.
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