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• W2103115912 abstract "This paper focuses on the characterization, modeling, and design of electrostatic discharge (ESD) protection devices such as the gated diode, the bulk substrate diode, and the double-well field-effect diode (DWFED) in 45 nm silicon-on-insulator technology. ESD protection capabilities are investigated using very fast transmission line pulsing tests to predict a device's performance in charged device model (CDM) ESD events. Device capacitance, which is critical for high-speed input/output performance, is evaluated, and biasing schemes and processing techniques are proposed to reduce the parasitic capacitance during normal operating conditions. Technology computer-aided design simulations are used to interpret the physical effects. The implementation of devices for meeting CDM protection requirements is discussed. Evaluation results identify DWFED as a promising candidate for the pad-based local-clamping scheme." @default.
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• W2103115912 date "2010-03-01" @default.
• W2103115912 modified "2023-09-27" @default.
• W2103115912 title "Design and Characterization of ESD Protection Devices for High-Speed I/O in Advanced SOI Technology" @default.
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• W2103115912 doi "https://doi.org/10.1109/ted.2009.2039524" @default.
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