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• W2109259551 abstract "We consider systems on chips (SoCs) that will be designed and produced in five to ten years from today, with gate lengths in the range 50-100nm. We address the distinguishing features of a design methodology that aims at achieving reliable designs under the limitations of the interconnect technology. Specifically, we consider energy consumption reduction, under guaranteed quality of service (QoS), as a main objective in system design." @default.
• W2109259551 created "2016-06-24" @default.
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• W2109259551 date "2001-01-01" @default.
• W2109259551 modified "2023-10-18" @default.
• W2109259551 title "Powering networks on chips" @default.
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• W2109259551 doi "https://doi.org/10.1145/500001.500009" @default.
• W2109259551 hasPublicationYear "2001" @default.
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