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• W2527831569 abstract "Full adder cells play a vital role in numerous VLSI circuits. Therefore, design of an energy-efficient full adder which operates reliably in submicron technologies has become a great concern in recent years. Some previously designed cells suffer from non-full swing outputs, high-power consumption and low-speed issues. In this paper, two high-speed, low-power and full-swing full adder circuits are designed in 90-nm CMOS technology. According to simulation results, the proposed circuits have rail to rail output signals. Also, an improvement of 12%–52%, 7%–48% and 28%–68% has been achieved in delay, power consumption and power-delay product (PDP), respectively." @default.
• W2527831569 created "2016-10-14" @default.
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• W2527831569 date "2016-05-01" @default.
• W2527831569 modified "2023-09-26" @default.
• W2527831569 title "Two new energy-efficient full adder designs" @default.
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• W2527831569 doi "https://doi.org/10.1109/iraniancee.2016.7585603" @default.
• W2527831569 hasPublicationYear "2016" @default.
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