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- Q59893327 description "article scientifique publié en 2018" @default.
- Q59893327 description "im Februar 2018 veröffentlichter wissenschaftlicher Artikel" @default.
- Q59893327 description "wetenschappelijk artikel" @default.
- Q59893327 description "наукова стаття, опублікована в лютому 2018" @default.
- Q59893327 name "An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA" @default.
- Q59893327 name "An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA" @default.
- Q59893327 type Item @default.
- Q59893327 label "An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA" @default.
- Q59893327 label "An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA" @default.
- Q59893327 prefLabel "An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA" @default.
- Q59893327 prefLabel "An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA" @default.
- Q59893327 P1433 Q59893327-3A7114E7-0ABB-4BDD-BFCB-4AFF82F8E259 @default.
- Q59893327 P1476 Q59893327-A22BC70B-65FB-4D7C-8F60-99EBF2B04DCF @default.
- Q59893327 P2093 Q59893327-5F7EDD0F-3BF5-4FA9-B84C-14A581129C69 @default.
- Q59893327 P304 Q59893327-1E64AC2D-F5D5-40C9-9405-189F11D576D9 @default.
- Q59893327 P31 Q59893327-AAC1A147-B9BA-4253-B0D7-EEF959D6EAAF @default.
- Q59893327 P356 Q59893327-792CA4C6-94B6-48EF-955D-B45937A9AA56 @default.
- Q59893327 P433 Q59893327-F87A9AE9-A9AC-482B-B54B-70C7699AA40C @default.
- Q59893327 P478 Q59893327-10FD5A17-5E62-4255-81D5-7917FC6E497B @default.
- Q59893327 P50 Q59893327-CD37DB1C-E7A6-4C9B-86C1-1F5F20264F6A @default.
- Q59893327 P577 Q59893327-87F681E4-E21C-4D81-97A9-BED5AA6441E2 @default.
- Q59893327 P8978 Q59893327-8387A833-6983-4979-BB20-137225CE04C1 @default.
- Q59893327 P356 TIM.2017.2769239 @default.
- Q59893327 P8978 ZhangZ18 @default.
- Q59893327 P1433 Q15751154 @default.
- Q59893327 P1476 "An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA" @default.
- Q59893327 P2093 "Dongming Zhou" @default.
- Q59893327 P304 "406-414" @default.
- Q59893327 P31 Q13442814 @default.
- Q59893327 P356 "10.1109/TIM.2017.2769239" @default.
- Q59893327 P433 "2" @default.
- Q59893327 P478 "67" @default.
- Q59893327 P50 Q59867832 @default.
- Q59893327 P577 "2018-02-01T00:00:00Z" @default.
- Q59893327 P8978 "journals/tim/ZhangZ18" @default.