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• W100281337 abstract "Testing of combinational circuit is crucial important to ensure high level of functionality. As density of digital circuit increases rapidly day by day these increases cost and time to test a particular combinational circuit for testing such circuit we need high quality test vector pattern with minimum number of input combination. In this work, we are designing Automatic test pattern generator (ATPG) D_Algorithm which will generate a minimum number of input pattern to detect fault like stuck-at-0 fault, stuck-at-1 fault, short circuit fault. D_Algorithm has been design by writing practical extraction and report language script to generate VHDL coding which is simulated on Xilinx 9.1." @default.
• W100281337 created "2016-06-24" @default.
• W100281337 creator A5020815692 @default.
• W100281337 creator A5071126961 @default.
• W100281337 date "2014-11-19" @default.
• W100281337 modified "2023-09-24" @default.
• W100281337 title "Implementation of Combinational Automatic Test Pattern Generator D_Algorithm" @default.
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• W100281337 hasPublicationYear "2014" @default.
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