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• W1027116203 abstract "ABSTRACT This paper presents an efficient method to designcascaded Σ∆ modulators implemented withcontinuous-time circuits. Instead of using adiscrete-to-continuous time transformation, the proposedmethodology is based on the direct synthesis of the wholecascaded architecture. This leads to more efficienttopologies in terms of circuit complexity, powerconsumption and robustness with respect to parasitics. Asan application, new cascaded topologies are synthesizedand optimized to cope with VDSL specifications. (*) 1. INTRODUCTION Sigma-Delta Modulators ( Σ∆Μs) have demonstratedto be an attractive solution for the implementation ofAnalog-to-Digital (A/D) interfaces in systems-on-chipintegrated in deep-submicron standard CMOStechnologies [1]. Although most reported Σ∆Ms havebeen implemented using Discrete-Time (DT) circuits, theincreasing demand for broadband data communicationsystems has motivated the use of Continuous-Time (CT)techniques. In addition to provide an intrinsic antialiasingfiltering, CT Σ∆Ms provide potentially faster operationwith lower power consumption than their DT counterparts[2][3].In spite of their mentioned advantages, CT Σ∆Ms aremore sensitive than DT Σ∆Ms to some circuit errors,namely: clock jitter, excess loop delay and technologyparameter variations [2][3]. The latter are speciallycritical for the realization of cascaded architectures. Thishas forced the use of single-loop topologies in mostreported silicon prototypes even thought lowoversampling ratios ( ) are needed [4][5], whereasfew cascaded CT Σ∆M Integrated Circuits (ICs) havebeen reported [6].However, the need to achieve medium-highresolutions ( ) within high signal bandwidths( ) while guaranteeing stability, has promptedthe development of several theoretical studies on thesynthesis of high-order cascaded CT Σ∆Ms [7][8][9].These studies are based on applying a DT-to-CTtransformation to an equivalent DT topology that fulfilsthe required specifications. In most cases, the use of sucha transformation is normally translated into a high numberof analog components, with the subsequent increase ofarea and power consumption.This paper describes a direct synthesis method whichbased on dispensing with the DT-to-CT equivalence,allows to reduce the number of analog components and toefficiently place the zeroes/poles of the loop-filter transferfunction, thus yielding to more robust CT cascaded Σ∆Msthan using a DT-to-CT transformation. As an application,the proposed methodology is used to synthesize optimumcascaded topologies intended for VDSL, targeting resolution within a signal bandwidth." @default.
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• W1027116203 date "2004-11-01" @default.
• W1027116203 modified "2023-09-24" @default.
• W1027116203 title "A New Method for the High-Level Synthesis of Continuous-Time Cascaded ΣΔ Modulators" @default.
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