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- W1036381839 abstract "In most cases ringing of the power supply is the major source of substrate noise generation, as shown in chapter 2. Techniques targeting at changing the shape of the supply current or its transfer function to the substrate can reduce substrate noise generation significantly. This chapter describes such reduction techniques, which modify the supply current and its transfer function. A mixed-signal ASIC was fabricated in a 0.35μ CMOS-EPI process in order to evaluate these low-noise design techniques. The test chip contains one reference design and two digital low-noise designs with the same basic architecture and functionality. Measurements show more than a factor of 2 on average in RMS noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of two reduction in RMS noise, with however a 70% increase in area but with a 5% decrease in power consumption." @default.
- W1036381839 created "2016-06-24" @default.
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- W1036381839 date "2006-05-30" @default.
- W1036381839 modified "2023-10-02" @default.
- W1036381839 title "Low-Noise Digital Design Techniques" @default.
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- W1036381839 doi "https://doi.org/10.1007/0-306-48170-7_11" @default.
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