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- W10797464 abstract "In this chapter, we propose a design and verification environment for computational demanding and secure embedded vision-based systems. Starting with an executable specification in OpenCV, we provide subsequent refinements and verification down to a system-on-chip prototype into an FPGA-based smart camera. At each level of abstraction, properties of image processing applications are used along with structure composition to provide a generic architecture that can be automatically verified and mapped to a lower abstraction level, the last of which being the FPGA. The result of this design flow is a framework that encapsulates the computer vision library OpenCV at the highest level, integrates Accelera’s SystemC/TLM with the Universal Verification Methodology (UVM) and QEMU-OS for virtual prototyping, verification, and low-level mapping." @default.
- W10797464 created "2016-06-24" @default.
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- W10797464 date "2014-01-01" @default.
- W10797464 modified "2023-10-16" @default.
- W10797464 title "Design and Verification Environment for High-Performance Video-Based Embedded Systems" @default.
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- W10797464 doi "https://doi.org/10.1007/978-1-4614-7705-1_4" @default.
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