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• W109799891 abstract "While performance and area remain to be two major design goals, power consumption has become a critical concern in today's VLSI system design. Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers have large area, long latency and consume considerable power. Previous work on low-power multipliers focuses on low-level optimizations and has not considered well the arithmetic computation features and application-specific data characteristics. At the algorithm and architecture level, this dissertation addresses low-power multiplier design systematically from two aspects: internal efforts considering multiplier architectures and external efforts considering input data characteristics. For internal efforts, we consider recoding optimization for partial product generation, operand representation optimization, and structure optimization of partial product reduction. For external efforts, we consider signal gating to de-activate portions of a full-precision multiplier. Several multiplier types are studied: linear array multipliers, leapfrog array multipliers, left-to-right linear array multipliers, split array multipliers, and tree multipliers. Experiments show that recoding optimization and structure optimization have achieved steady power reduction with reduced delay for both random test data and large-dynamic-range data. Operand representation optimization and signal gating have demonstrated significant power saving for large-dynamic-range data with relatively small overhead." @default.
• W109799891 created "2016-06-24" @default.
• W109799891 creator A5004115757 @default.
• W109799891 creator A5023679657 @default.
• W109799891 date "2003-01-01" @default.
• W109799891 modified "2023-09-23" @default.
• W109799891 title "High-level optimization techniques for low-power multiplier design" @default.
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