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- W121208955 abstract "Data insensitive controllers (DICs) are systems where the datapath consists of assignment gates moving the integer data around, and latches storing the data. Memory controllers and communication systems are examples of DICs. In [HB95], it is proved that for DICs the property “when binary variable b becomes true, integer variables x and y are equal” can be proved by down-scaling the integer variables x and y to single-bit binary variables. In this paper, we generalize this notion and consider the problem of verifying properties of DICs in a linear temporal logic whose atomic propositions are finite variables and integer equalities. We show that for this temporal logic, one can always use finite instantiations, although the number of required bits varies with the complexity of the property.KeywordsFormal verificationComputer-aided designverification." @default.
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- W121208955 date "1997-01-01" @default.
- W121208955 modified "2023-09-26" @default.
- W121208955 title "Verifying linear temporal properties of data insensitive controllers using finite instantiations" @default.
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- W121208955 doi "https://doi.org/10.1007/978-0-387-35064-6_5" @default.
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