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- W131449649 abstract "Abstract — An efficient ASIC chip of the Golay codec has been designed for channel coding. This paper describes the new architecture used in this chip and the ASIC design. Due to the new architecture which implements a permutation decoding algorithm based on a new minimum permutation set proposed by [6], the codec architecture is relatively simple and a higher speed of the decoding procedure can be achieved compared with the Golay decoder of the decoding algorithms in common use, error-trapping algorithm and step-by-step method. From [7], Kasami's error-trapping decoder requires 46 shift-operations for decoding one completely received word and the modified step-by-step decoder[7] requires 35 shift operations, while our decoder requires only 14 permutation operations, generalized shift operations. Consequently, this decoder can work faster than the Kasami's error-trapping decoder and the modified step-by-step decoder[7]." @default.
- W131449649 created "2016-06-24" @default.
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- W131449649 date "1992-01-01" @default.
- W131449649 modified "2023-10-15" @default.
- W131449649 title "A CODEC CHIP ARCHITECTURE FOR (24,12,8) GOLAY CODE WITH THE PERMUTATION DECODING" @default.
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- W131449649 doi "https://doi.org/10.1016/b978-0-444-89587-5.50092-x" @default.
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