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- W134476543 abstract "Multiform logical time, introduced and made popular through its central role in Synchronous Language theory, is already present in many formalisms pertaining to embedded system design, although usually in a hidden fashion. Logical time considers time bases that can be generated from any sort of sequences of events, not necessarily equally spaced in physical time. Our main goal here is to capture some of the essence of multiform logical time, and encapsulate it into a dedicated syntax (CCSL, Clock Constraint Specification Language, part of the UML profile for MARTE). CCSL provides ways to express loose or strict constraints between distinct logical clocks. Solving such clock constraints amounts to relating clocks to a common reference one, which then can be thought of as closer to physical. We motivate the role of MARTE Time Model and CCSL by using them to explain and formally characterize important semantic features of East-ADL/AUTOSAR, AADL, and Ptolemy’s SDC models." @default.
- W134476543 created "2016-06-24" @default.
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- W134476543 date "2010-01-01" @default.
- W134476543 modified "2023-10-18" @default.
- W134476543 title "The Time Model of Logical Clocks Available in the OMG MARTE Profile" @default.
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- W134476543 doi "https://doi.org/10.1007/978-1-4419-6400-7_7" @default.
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