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• W138962311 abstract "We describe and evaluate a template architecture for SoC systems intended for multimedia applications. The architecture is a 2-level hierarchy that consists at the bottom level of several processing units (PUs), controlled at the top level by a control processor. The main characteristic of our architecture is that it exploits in hardware parallelism among tasks executing on dieren t PUs in the same way a superscalar processor exploits instruction level parallelism. This hardware support for task-level parallelism gives rise to a natural programming model that relieves programmers from explicitly synchronizing tasks and communicating data. We describe a number of code transformations to improve performance that are based on well-known compiler analyses, and thus can be incorporated into a compiler for this architecture. We use simulation, two realistic multimedia applications and the proposed code transformations to explore the performance vs. resources trade-o." @default.
• W138962311 created "2016-06-24" @default.
• W138962311 creator A5004658137 @default.
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• W138962311 date "2003-01-01" @default.
• W138962311 modified "2023-09-27" @default.
• W138962311 title "The Hyperprocessor: A Template System-on-Chip Architecture for Embedded Multimedia Applications" @default.
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