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- W1485350918 abstract "As VLSI circuitry advances to deep sub-micron (DSM) dimensions and operates at giga-Hertz clock frequencies, interconnect has become the dominating factor in determining the overall system performance, cost and reliability. This dissertation studies five related research topics in an interconnect-centric design flow which covers interconnect synthesis and interconnect planning. In the interconnect synthesis framework at the layout optimization level, we study two research topics focusing on the coupling capacitance, which has now becomes the dominant component for the interconnect delay and the crosstalk noise: (i) We formulate the interconnect sizing and spacing problem with consideration of coupling capacitance, and develop very effective algorithms for performance optimization. (ii) We also develop a much improved crosstalk noise model for interconnect optimization and use it to guide noise-aware interconnect optimization. In the interconnect planning framework at broad abstraction levels from physical layout to architecture planning, we present our findings on three related research topics: (i) We develop the first comprehensive set of interconnect performance estimation models to predict the interconnect behavior under different optimization methods. Our models can achieve about 90% accuracy, and run 10,000x faster than performing the real optimization. (ii) In the architecture-level interconnect planning, we present a systematic wire width planning methodology and show that two pre-determined wire widths per metal layer are sufficient to achieve near-optimal performance for current and future technology generations. This result will significantly simplify the routing architecture. (iii) In the physical-level interconnect planning, we first formulate the problem of buffer block planning and introduce a new concept of feasible region for buffer insertion. We derive analytical formulae for the feasible region and develop an effective algorithm for buffer block planning." @default.
- W1485350918 created "2016-06-24" @default.
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- W1485350918 date "2000-01-01" @default.
- W1485350918 modified "2023-09-23" @default.
- W1485350918 title "Interconnect synthesis and planning for high-performance ic designs" @default.
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