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- W1485497639 abstract "Unification is one of the most important processes in Prolog systems. In this paper, We propose a dedicated hardware unifier consisting of four stages of pipelined processors, which find variable bindings known as ‘mgu’. To achieve pipelining, terms are expressed especially by a sequence of symbols with their arities. To enhance its performance, only terms which are bound by variables are managed within this unifier, and the structure sharing method is also adopted to prevent the occurrence of redundancy of variables. Moreover ‘occur-check’, which is known to be a heavy load on software systems, is easily performed during unification." @default.
- W1485497639 created "2016-06-24" @default.
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- W1485497639 date "1988-01-01" @default.
- W1485497639 modified "2023-09-27" @default.
- W1485497639 title "The Unification Processor by Pipeline Method" @default.
- W1485497639 cites W2113722134 @default.
- W1485497639 doi "https://doi.org/10.1007/978-1-4613-1679-4_45" @default.
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