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- W1486604992 abstract "Genesil was embedded into a VHDL environment in order to support early tradeoffs between ASICs, standard parts and software. A common front end is used to create RTL chip models in VHDL and to drive Genesil. The VHDL-Genesil interface supports use of multiple models with increasing detail and timing back-annotation. Examples are reported of automatically generated VHDL models." @default.
- W1486604992 created "2016-06-24" @default.
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- W1486604992 date "1990-09-01" @default.
- W1486604992 modified "2023-09-24" @default.
- W1486604992 title "A Top-Down VHDL Interface to the Genesil Silicon Compilation System" @default.
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