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- W1488775163 abstract "We proposed a novel architecture of finite field multiplier over GF(2m). The architecture applied Karats algorithm, which reduced the needed number of multiplication. It also made use of shifted irreducible polynomial, which reduced the critical path delay without increasing output latency. Although the implementation seemed some complicated considering the control logic needed, the design of control logic was not difficult and its cost was taken into account to make it fair when comparing performance with other method. The FPGA experiment result showed that the performance is better than other typical digit-serial multiplier both in area and frequency. It may benefit Elliptic Curve Cryptography applications." @default.
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- W1488775163 date "2012-10-16" @default.
- W1488775163 modified "2023-09-23" @default.
- W1488775163 title "Efficient FPGA Implementation of Multiplier over GF (2m)" @default.
- W1488775163 doi "https://doi.org/10.1109/icecc.2012.90" @default.
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