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- W1489308954 abstract "This paper describes CMOS Pass-gate No-race Charge-recycling Logic (CPNCL). CPNCL realizes low power computation by using a charge sharing method without pre-evaluation problems. CPNCL operates in push-pull mode using CMOS pass-gate logic. 2-input NAND CPNCL shows about 30-50% improvement in power-delay product over other logics. The operation and characteristics of CPNCL are verified by the implementation of a 32 bit adder. CPNCL is more effective than other charge recycling logics in the implementation of a large fan-in random function with arbitrary signal arriving." @default.
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- W1489308954 date "2003-01-20" @default.
- W1489308954 modified "2023-09-23" @default.
- W1489308954 title "CMOS Pass-gate No-race Charge-recycling Logic (CPNCL)" @default.
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- W1489308954 doi "https://doi.org/10.1109/iscas.1999.777844" @default.
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