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- W148970219 abstract "Techniques for reducing power consumption and bandwidth limitations of inter-chip communication have been getting more attention to improve the performance of modern digital systems. This chapter begins with a brief overview of high-speed link design and describes some of the power vs. performance trade-offs associated with various design choices. The chapter then investigates various techniques that a designer may employ to reduce power consumption. Three examples of link designs and link building blocks found in the literature present energy-efficient implementations of these techniques." @default.
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- W148970219 date "2006-01-02" @default.
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- W148970219 title "Energy-Efficient Design of High-Speed Links" @default.
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- W148970219 doi "https://doi.org/10.1007/0-306-48139-1_8" @default.
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