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- W1491135237 abstract "Abstract : This research effort considers heuristic and cost model based techniques for the optimal partitioning of VHDL circuits for parallel simulation. Correlation statistics are gathered on a wide variety of graph-based a priori parameters. Linear regression is used to identify significant parameters for inclusion in a representative cost model. Driving a greedy search, this cost model is used to improve upon initial heuristic partitions. The influence of feedback dominated previous research so a no-feedback algorithm is used to create the initial partition The circuits studied range from 1,050 to 4,243 gates." @default.
- W1491135237 created "2016-06-24" @default.
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- W1491135237 date "1994-12-01" @default.
- W1491135237 modified "2023-09-24" @default.
- W1491135237 title "Accelerating Conservative Parallel Simulation of VHDL Circuits" @default.
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