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- W1492547117 abstract "Abstract Formal verification methods provide a way to prove that a circuit structure correctly implements its specification. Low level gate and transistor logic circuits can be verified using methods such as symbolic simulation. Higher level circuits can be verified using theorem-proving methods, providing a multi-leveled approach to complex device verification. Correct modeling of many VLSI circuits requires a signal value data type that includes some degree of strength indeterminacy. The VHDL Standard Logic Package includes such a signal value data type, t_wlogic, that includes 46 unique values. In this paper we provide a foundation for the t_wlogic values and their resolution function that provides a possible link between simulation and theorem-proving. A formalization of the low level signal values used by design tools also facilitates reasoning about CAD tools." @default.
- W1492547117 created "2016-06-24" @default.
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- W1492547117 date "1993-01-01" @default.
- W1492547117 modified "2023-09-27" @default.
- W1492547117 title "REASONING ABOUT THE VHDL STANDARD LOGIC PACKAGE SIGNAL DATA TYPE" @default.
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- W1492547117 doi "https://doi.org/10.1016/b978-0-444-81641-2.50014-9" @default.
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