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• W1493217096 abstract "Non zero signal rise and fall times significantly contribute to the gate propagation delay. Designers must accurately consider them when defining timing library format. Based on a design oriented macro-model of the timing performance of CMOS structures, we present in this paper a general representation of transition times allowing fast and accurate cell performance evaluation. This general representation is then exploited to define a robust characterization protocol of the output transition time of standard cells. Both the representation and the protocol are finally validated comparing calculated gate input-output transition time values with standard look-up representation obtained from Hspice simulations (Bsim3v.3, level 69, 0.25µm process)." @default.
• W1493217096 created "2016-06-24" @default.
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• W1493217096 date "2002-01-01" @default.
• W1493217096 modified "2023-09-23" @default.
• W1493217096 title "Structure Independent Representation of Output Transition Time for CMOS Library" @default.
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• W1493217096 doi "https://doi.org/10.1007/3-540-45716-x_25" @default.
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