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- W1495620715 abstract "In this paper, we propose a 4/spl times/4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders, which adopt macroblock level pipelines, our proposed 4/spl times/4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260000 MB/s under 100 MHz clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920/spl times/1088) video sequence in 30fps (244800 MB/s required) and level 4 of baseline profile." @default.
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- W1495620715 date "2005-07-27" @default.
- W1495620715 modified "2023-09-26" @default.
- W1495620715 title "An H.264/AVC Decoder with 4X4-Block Level Pipeline" @default.
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- W1495620715 doi "https://doi.org/10.1109/iscas.2005.1464961" @default.
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