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• W1496757799 abstract "The high performance potential of an FPGA is not fully exploited if a design suffers a memory bottleneck. Therefore, a memory hierarchy is needed to reuse data in on-chip buffer memories and minimize the number of accesses to off-chip memory. Buffer memories not only hide the external memory latency, but can also be used to remap data and augment the on-chip bandwidth through parallel access of multiple buffers. This paper discusses the differences and similarities of memory hierarchies on processor- and on FPGA-based systems and presents a step-by-step methodology to construct a memory hierarchy on an FPGA." @default.
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• W1496757799 date "2011-01-01" @default.
• W1496757799 modified "2023-09-23" @default.
• W1496757799 title "Constructing Application-Specific Memory Hierarchies on FPGAs" @default.
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• W1496757799 doi "https://doi.org/10.1007/978-3-642-19448-1_11" @default.
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