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• W1496858358 abstract "This paper proposes an FPGA architecture for the 1-D forward integer transform of the High Efficiency Video Coding (HEVC), which is the latest video coding standard. The work presents a novel technique which makes the architecture able to compute transform of flexible input combinations. The architecture can support all transform sizes i.e. 4×4, 8×8, 16×16, and 32×32, and all possible input combinations resulting from a residual quad-tree partitioning with uniform throughputs. Configuration encoding scheme is invented to efficiently represent input combinations. The design gives a high throughput of 1,640 Msamples/s independent of input combination, which is sufficient to encode 8K (7680×4320) videos in real-time, 30 fps." @default.
• W1496858358 created "2016-06-24" @default.
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• W1496858358 date "2015-06-01" @default.
• W1496858358 modified "2023-09-26" @default.
• W1496858358 title "Flexible input transform architecture for HEVC encoder on FPGA" @default.
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• W1496858358 doi "https://doi.org/10.1109/ecticon.2015.7206947" @default.
• W1496858358 hasPublicationYear "2015" @default.
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