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- W1496887259 abstract "In this paper, a low power synthesizable register file architecture is presented. The register file is modeled on register-transfer level (RTL). It is suitable for technology independent IP-core and processor models. The data inputs of all registers of the register file are connected to a data bus. Similar to operand isolation for combinational logic blocks we use blocking logic in order to isolate registers from transitions on the data bus. The registers are divided into groups and blocking logic is inserted for each group. Even if no spurious transitions occur on the data bus, the power dissipation of the register file can be reduced applying this register file architecture." @default.
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- W1496887259 date "2004-01-01" @default.
- W1496887259 modified "2023-09-27" @default.
- W1496887259 title "Register Isolation for Synthesizable Register Files" @default.
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- W1496887259 doi "https://doi.org/10.1007/978-3-540-30205-6_25" @default.
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