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- W1497282068 abstract "Synchronous reactive systems (SRS) form a convenient description model of controllers, either software or hardware. They are based on finite state Mealy machine interpretation, and languages such as ESTEREL or LUSTRE allow for their structured programming, including parallel subcomponents. Internal formats such as BLIF provide intermediate description at the level of boolean equations, in which both output signal and resulting latch values are expressed as propositional formulae on input signals and previous latch values. ESTEREL also produces its own such format, named sc format. SRSs allow powerful programming of reactive systems, using synchronous parallelism as the core modularity feature, and signal diffusion for instantaneous communication. The impact for this programming style was amply demonstrated elsewhere. As a trade-off to this expressiveness, ESTEREL programs may suffer of hazards: signals may sometimes be emitted as a result of their presence (or absence). Correct ESTEREL programs are those respecting a constructive causality criterion. In addition, there exist the same classical demand for verification and model-based analysis as in other concurrency domains. Due to implicit parallelism of latches the number of reachable configurations, while finite, may grow very large. Computation of this state space is an important first step for verification, or generally speaking in analysis of SRSs. Proper or other correctness criteria need only to hold inside this reachable domain; once computed it can be used as the basis for a number of further inquiries. We shall demonstrate two tools for analysis of boolean equation systems as obtained from ESTEREL, and using efficient symbolic state space construction from the BDD package TIGER: SCCAUSAL deals specifically with issues, while BLIFFC2 performs model-based verification and automata minimieation. We tackle the important problem of counterexample recovery at source code level, where we (re)use the XES graphical simulation interface for ESTEREL. Symbolic execution paths leading to problematic configurations are automatically produced, and animated graphically by the simulator. We use as a running example a simple hardware bus arbiter (taken and simplified from K. Mc Millan's thesis)." @default.
- W1497282068 created "2016-06-24" @default.
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- W1497282068 date "1996-01-01" @default.
- W1497282068 modified "2023-09-24" @default.
- W1497282068 title "Verifying synchronous reactive systems programmed in ESTEREL" @default.
- W1497282068 cites W4246404081 @default.
- W1497282068 doi "https://doi.org/10.1007/3-540-61648-9_57" @default.
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