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- W1497483492 abstract "A low-power parallel VLSI structure for DCT/IDCT is proposed. By treating the transformations as the evaluation of the Chebyshev series, and exploiting the Backward Chebyshev Recursion (BCR), we can reduce the total number of multipliers (N+1 for IDCT, 2N-2 for DCT). The property of BCR is also used to compute the DCT/IDCT through the down-sampled even and odd sequences. Since the operation frequency for the down-sampled sequences is two times slower, the speed penalty caused by the low-voltage design can be compensated at the architectural level. The total multipliers required for the low-power design is only 2N+1 for IDCT and 3N-3 for DCT. Extension to downsampling-by-4 is also achievable at a reasonable increase in hardware complexity. >" @default.
- W1497483492 created "2016-06-24" @default.
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- W1497483492 date "2002-12-17" @default.
- W1497483492 modified "2023-09-25" @default.
- W1497483492 title "A low-power and low-complexity DCT/IDCT VLSI architecture based on backward Chebyshev recursion" @default.
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- W1497483492 doi "https://doi.org/10.1109/iscas.1994.409221" @default.
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