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• W149975372 abstract "In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive and time-consuming nanolithography such as E-beam lithography. The capability to fabricate nano-scale dimension structures at wafer level without the above-mentioned technology is essential for both cost reduction and decrease of processing complexity (Chapter 2). In this sense, processing methods and techniques used in semiconductor-(silicon-) based microfabrication (e.g. Micro-ElectroMechanical Systems or MEMS technology) provide a good toolbox to work with. Major challenges remain in finding a simple, yet reliable large-scale device processing/fabrication technique, getting a good electrical contact between the nano-scale device and the outside world, easy integration and advanced packaging of the whole system for better electronics read-out. While bottom-up approaches have their own merits (e.g. bundles of devices), the top-down approach offers ease of assembling, contact characterization and advanced packaging. In this thesis, we studied and compared the state-of-the-art techniques and methods that are available in the literature in answering the “know-how” question of fabricating/defining SiNWs and their advantages with a focus on wafer-scale fabrication and biosensing applications. This overview and discussion are presented in Chapter 2. In Chapter 3, several different top-down approaches for wafer-scale fabrication of SiNW FETs are proposed and implemented. The developed technology, including the innovative steps and considerations involved are extensively described. Three process flow schemes are defined. The first one is for the fabrication of nanosheet FETs using standard photolithography, namely a UV lithography wafer stepper available in our DIMES clean room. By tuning and optimizing the energy dose applied and the focus values used through internal optics of the stepper, the 500 nm width (which is the nominal minimum exposed line width) could be reduced to 250 nm. However, before exposing the wafer, frequent calibration of the exposure energy and focus optimization are necessary each time. This resulted in a time-consuming and complex process. To reduce this complexity, a new platform for low-cost, room-temperature processing was developed. The method is based on MEMS technology and takes advantage of the etch dependence on lattice orientation of single-crystalline silicon. The concept of “shrinking the big ones” is adapted in this process where we started from a wide line/slab and subsequently reduced it to a SiNW by using a commonly available photoresist developer (AZ 400K, 15% of potassium borate in water). With a correct alignment to the Si lattice and the slow etching rate of the photoresist developer, similar facets SiNW FETs (sidewalls and top surface) of single and arrays of SiNWs can be obtained. Moreover, straight and smooth sidewalls of the SiNW are also obtained. The third method is based on the uniform deposition of materials across the wafer where the deposited material thickness defines the width of the SiNW. The dry etching procedure is highly directional, thus while the areas perpendicular to the planar surface are fully removed, the material deposited on the sidewalls is hardly etched. The remaining sidewalls form the hard mask in defining the SiNW FETs. SiNWs defined with this method show a higher uniformity compared to the developer etching process. Electrical characterization of all fabricated SiNW FETs devices are performed and discussed in Chapter 4. SPECTRA device simulator from Link Research Incorporation, Japan is used to simulate the electrical behavior of the SiNW FETs under a steady-state condition. The characterized devices with gate terminal situated at the backside of the chip behave as per expected (i.e. p-type MOSFET behavior). The fixed oxide charges in the oxide layer deposited on the SiNW FETs do affect the device performance. The contact resistance (outside of SiNW FETs) is estimated using the so-called Transfer Length Method (TLM) and contributes to less than 1% of the total resistance measured. Noise levels, which are crucial in differentiating the changes from the background, are also studied in relation to the fabrication and etching method used. Similar (in dimension and doping concentration) devices from developer-etched and plasma-etched devices are studied and their performance has been compared. Noise levels from devices made via the developer-etching method are at least an order of magnitude lower than those prepared via the plasma-etching approach. This indicates that devices etched with a wet developer have a higher signal-to-noise ratio and a lower detection limit for bio-sensing applications. The performance of our fabricated SiNW FETs in the aqueous environment is investigated. Several types of experiments are performed: changing the pH of the aqueous solution, layer-by-layer deposition of oppositely charged polyelectrolytes and finally, preliminary experiments on the detection of antigens related to influenza virus A were performed, as shown and discussed in Chapter 5. In the pH measurements the silicon nanowires were in a dual-gate configuration and showed a change of about 50 mV/pH of back-gate electrode in order to maintain the source-drain current at a fixed source-drain voltage, which shows good pH sensitivity. Layer-by-layer deposition of the alternating charged polyelectrolytes showed an alternating change of the back-gate voltage to maintain the source-drain current at a fixed source-drain potential and the result is comparable to responses reported in the literature. In the preliminary experiments of using SiNW FETs for the detection of antigens related to influenza virus A, no discrimination in response could be observed between antibody and non-antibody (as a control) modified nanowires. In conclusion, the proposed fabrication schemes for SiNW FETs indicate that it is possible to realize SiNWs with good uniformity and smooth surfaces while using wafer-scale and IC compatible technologies. The electrical characterization of the fabricated FETs suggests that these devices are very promising as sensors. Further process optimization for the fabrication or definition method of SiNW FETs of the current process flow is anticipated and suggestions on how to address this are presented in Chapter 6. In addition, possible topics for future work are briefly addressed. Finally, the presented SiNW FETs could be used as a biosensor for ultra-sensitive detection and at the same time address new challenges in the field of surface chemistry and biology." @default.
• W149975372 created "2016-06-24" @default.
• W149975372 creator A5065272651 @default.
• W149975372 date "2013-12-09" @default.
• W149975372 modified "2023-09-27" @default.
• W149975372 title "IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications" @default.
• W149975372 doi "https://doi.org/10.4233/uuid:5674b9ff-4ee7-4c74-8244-32384c6224d6" @default.
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