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- W1499853833 abstract "This paper describes experimental results used to optimize the source/drain implant design of a dynamic threshold DTMOS n-channel device, fabricated within a low-cost 0.15 /spl mu/m SOI CMOS System-On-Chip process, which also included high-density embedded DRAM. A shallower, lower dose S/D implant was found to lower the body resistance and DIBL, thus increasing the dynamic body effect. The DTMOS device design in this process was previously found to be superior to both grounded body (GB) and floating body (FB) operation, with Ion=56 uA//spl mu/m, Ioff=3 pA//spl mu/m, S=64 mV/dec, and Gm=1690 uS//spl mu/m at Vdd=1.0 V. This DTMOS device was also previously shown to have excellent analog and RF performance, with Fmax=32 GHz. These characteristics permit embedded ultra-low-voltage analog circuits and RF front-end circuits in combination with embedded DRAM cores for ultra-low-power, low-cost SOCs." @default.
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- W1499853833 date "2004-05-06" @default.
- W1499853833 modified "2023-09-25" @default.
- W1499853833 title "Source/drain optimization of the dynamic-threshold DTMOS device in a 0.15 μm SOI embedded DRAM technology" @default.
- W1499853833 cites W2059634421 @default.
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- W1499853833 doi "https://doi.org/10.1109/ugim.2003.1225758" @default.
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