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- W1501013951 abstract "The objective of the paper is to present a low power 4×4 digital multiplier design to reduce power consumption of digital multiplier based on 2-dimensional bypassing method. Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. The proposed bypass cells constitute the multiplier skip redundant signal transitions when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing architecture using which we designed a Digital filter for low power dissipation in signal processing applications. Thorough post-layout simulations show that the power dissipation of the proposed 2D multiplier and FIR filter design based on 2D multiplier is reduced by more than 75% compared to the prior design with obscure cost of delay and area." @default.
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- W1501013951 date "2011-01-01" @default.
- W1501013951 modified "2023-09-26" @default.
- W1501013951 title "A low power multiplier architecture based on bypassing technique for digital filter" @default.
- W1501013951 doi "https://doi.org/10.1049/cp.2011.0432" @default.
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