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- W1501405854 abstract "We propose sub-1Aring-order analysis of gate/insulator interfacial region in scaled-Tinv gate stacks by differentiating their C-V curves. By applying this technique to p+ poly-Si/HfSiON, it is found that gate depletion increases due to both lower poly impurity cone. (Npoly) and huge amount of pinning charge inside the dielectric (Nox). We found ultra-thin SiN cap insertion recovers the degradation in Npoly and Nox, leading to improvement of gate depletion and DeltaVjb. By analyzing FUSI stacks, absence of semiconducting interlayer is verified with sub-1Aring resolution, and it is also found that As segregation outside SiO2 leads to EOT increase as well as work function (WF) modulation in As-doped FUSI/SiO2, whereas As segregation inside HfSiON results in smaller WF change in FUSI/HfSiON" @default.
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- W1501405854 date "2006-10-24" @default.
- W1501405854 modified "2023-09-25" @default.
- W1501405854 title "Sub-1A-Resolution Analysis and Physical Understanding of Gate/Insulator Interfacial Region in Scaled-Tinv High-k Gate Stacks" @default.
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- W1501405854 doi "https://doi.org/10.1109/vlsit.2006.1705277" @default.
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