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• W1503451007 abstract "In areas of signal processing and communications such as antenna array beamforming,adaptive filtering, multi-user and multiple-input multiple-output (MIMO) detection, channelestimation and equalization, echo and interference cancellation and others, solving linearsystems of equations often provides an optimal performance. However, this is also avery complicated operation that designers try to avoid by proposing different sub-optimalsolutions. The dichotomous coordinate descent (DCD) algorithm allows linear systemsof equations to be solved with high computational efficiency. It is a multiplication-freeand division-free technique and, therefore, it is well suited for hardware implementation.In this thesis, we present architectures and field-programmable gate array (FPGA) implementationsof two variants of the DCD algorithm, known as the cyclic and leadingDCD algorithms, for real-valued and complex-valued systems. For each of these techniques,we present architectures and implementations with different degree of parallelism.The proposed architectures allow a trade-off between FPGA resources and the computationtime. The fixed-point implementations provide an accuracy performance which isvery close to the performance of floating-point counterparts.We also show applications of the designs to complex division, antenna array beamformingand adaptive filtering. The DCD-based complex divider is based on the ideathat the complex division can be viewed as a problem of finding the solution of a 2x2real-valued system of linear equations, which is solved using the DCD algorithm. Therefore,the new divider uses no multiplication and division. Comparing with the classicalcomplex divider, the DCD-based complex divider requires significantly smaller chip area.A DCD-based minimum variance distortionless response (MVDR) beamformer employsthe DCD algorithm for multiplication-free finding the antenna array weights. AnFPGA implementation of the proposed DCD-MVDR beamformer requires a chip areamuch smaller and throughput much higher than that achieved with other implementations.The performance of the fixed-point implementation is very close to that of floating-pointimplementation of the MVDR beamformer using direct matrix inversion. When incorporating the DCD algorithm in recursive least squares (RLS) adaptive filter,a new efficient technique, named as the RLS-DCD algorithm, is derived. The RLS-DCDalgorithm expresses the RLS adaptive filtering problem in terms of auxiliary normal equationswith respect to increments of the filter weights. The normal equations are approximatelysolved by using the DCD iterations. The RLS-DCD algorithm is well-suited tohardware implementation and its complexity is as low as O(N2) operations per sample ina general case and O(N) operations per sample for transversal RLS adaptive filters. Theperformance of the RLS-DCD algorithm, including both fixed-point and floating-pointimplementations, can be made arbitrarily close to that of the floating-point classical RLSalgorithm. Furthermore, a new dynamically regularized RLS-DCD algorithm is also proposedto reduce the complexity of the regularized RLS problem from O(N^3) to O(N^2) ina general case and to O(N) for transversal adaptive filters. This dynamically regularizedRLS-DCD algorithm is simple for finite precision implementation and requires small chipresources." @default.
• W1503451007 created "2016-06-24" @default.
• W1503451007 creator A5085352453 @default.
• W1503451007 date "2008-11-01" @default.
• W1503451007 modified "2023-09-22" @default.
• W1503451007 title "DCD algorithm : architectures, FPGA implementations and applications" @default.
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• W1503451007 hasPublicationYear "2008" @default.
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