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• W1504244237 abstract "We propose a novel dynamic voltage scaling (DVS) approach for reliable and energy efficient cache memories. First, we demonstrate that, as memories age, leakage power reduction techniques become more effective due to sub-threshold current reduction with aging. Then, we provide an analytical model and a design exploration framework to evaluate trade-offs between leakage power and reliability, and propose a BTI and leakage aware selection of the “drowsy” state retention voltage for DVS of cache memories. We propose three DVS policies, allowing us to achieve different power/reliability trade-offs. Through SPICE simulations, we show that a critical charge and a static noise margin increase up to 150% and 34.7%, respectively, is achieved compared to standard aging unaware drowsy technique, with a limited leakage power increase during the very early lifetime, and with leakage energy saving up to 37% in 10 years of operation. These improvements are attained at zero or negligible area cost." @default.
• W1504244237 created "2016-06-24" @default.
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• W1504244237 date "2015-07-01" @default.
• W1504244237 modified "2023-09-25" @default.
• W1504244237 title "BTI and leakage aware dynamic voltage scaling for reliable low power cache memories" @default.
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• W1504244237 doi "https://doi.org/10.1109/iolts.2015.7229858" @default.
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