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• W1505936290 abstract "This paper presents a novel DFT method which requires very small modification to a controller in RT-level description of a circuit. The control/data flow graph (CDFG) representation of an RTL circuit is used for analyzing the testability of individual RT-level operations within a hierarchical test technique. Using a non-scan arrangement, existing data paths are utilized to provide controllability and observability to RT-level operations. Furthermore, additional data paths are introduced by altering the controller states or signals. Post behavioral synthesis information and pre-computed test vectors of the individual modules are utilized. This method considerably reduces the test application time by ignoring unnecessary control states in the test process" @default.
• W1505936290 created "2016-06-24" @default.
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• W1505936290 date "2005-12-13" @default.
• W1505936290 modified "2023-09-23" @default.
• W1505936290 title "A Flow Graph Technique for DFT Controller Modification" @default.
• W1505936290 cites W1560178046 @default.
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• W1505936290 doi "https://doi.org/10.1109/socc.2005.1554454" @default.
• W1505936290 hasPublicationYear "2005" @default.
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