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• W1506445585 abstract "With each new feature size, integrated circuit (IC) manufacturing costs increase. Rising expenses cause the once vertical IC supply chain to flatten out. Companies are increasing their reliance on contractors, often foreign, to supplement their supply chain deficiencies as they no longer can provide all of the services themselves. This shift has brought with it several security concerns classified under three categories: (1) Metering controlling the number of ICs created and for whom. (2) Theft controlling the dissemination of intellectual property (IP). (3) Trust controlling the confidence in the IC post-fabrication. Our research focuses on providing a solution to the metering problem by restricting an attacker’s access to the IC design. Our solution modifies the CAD tool flow in order to identify locations in the circuit which can be protected with reconfigurable logic barriers. These barriers require the correct key to be present for information to flow through. Incorrect key values render the IC useless as the flow of information is blocked. Our selection heuristics utilize observability and controllability don’t care sets along with a node’s location in the network to maximize an attacker’s burden while keeping in mind the associated overhead. We implement our approach in an open-source logic synthesis tool, compare it against previous solutions and evaluate its effectiveness against a knowledgeable attacker." @default.
• W1506445585 created "2016-06-24" @default.
• W1506445585 creator A5069873488 @default.
• W1506445585 date "2018-08-10" @default.
• W1506445585 modified "2023-09-25" @default.
• W1506445585 title "Preventing integrated circuit piracy using reconfigurable logic barriers" @default.
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• W1506445585 doi "https://doi.org/10.31274/etd-180810-363" @default.
• W1506445585 hasPublicationYear "2018" @default.
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