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- W1508331763 abstract "A new opamp with a short power-on time is used in a 10b 1.5b/stage power scalable pipelined ADC in 0.18 /spl mu/m CMOS. A current modulation technique is used so that as the power is varied from 15 /spl mu/W (at 1 kS/s) to 35 mW (at 50 MS/s) the bias currents only increase by a factor of 50. The SNDR is 54 to 56 dB for all sampling rates." @default.
- W1508331763 created "2016-06-24" @default.
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- W1508331763 date "2005-08-30" @default.
- W1508331763 modified "2023-09-26" @default.
- W1508331763 title "A 50MS/s (35mW) to 1ks/s (15μW) power scaleable 10b pipelined ADC with minimal bias current variation" @default.
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- W1508331763 doi "https://doi.org/10.1109/isscc.2005.1493978" @default.
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