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• W1509585227 abstract "A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both commercial and technical multiuser applications. Key performance features include a 3-ns, 32-b adder; low-skew on-chip clock buffers; and cycling off-chip caches at the operating frequency, using industry-standard synchronous static random-access memories (SRAMs). The speeds obtained are comparable to those of many emitter-coupled logic (ECL) implementations. The CPU chip includes the following hardware: integer fetch and execute unit, on-chip split I/D TLBs (translation lookaside buffers) with two-way 64 entries each, control for second-level off-chip TLBs, control for off-chip two-way split I/D writeback caches with single-bit error correction for data, full multiprocessing support hardware, inference for performance analysis and tuning, and a tightly coupled coprocessor interface. >" @default.
• W1509585227 created "2016-06-24" @default.
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• W1509585227 date "1990-01-01" @default.
• W1509585227 modified "2023-09-27" @default.
• W1509585227 title "A 90 MHz CMOS RISC CPU designed for sustained performance" @default.
• W1509585227 cites W1488934543 @default.
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• W1509585227 doi "https://doi.org/10.1109/isscc.1990.110125" @default.
• W1509585227 hasPublicationYear "1990" @default.
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