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- W1511039581 abstract "Good energy efficiency and area efficiency are both achieved for the presented 9-bit 35MS/s SAR ADC, by using customized small-value capacitors in a splitting monotonic switching scheme, a simplified dynamic digital logic and a self-clocked dynamic comparator. With built-in configurable gain, the ADC maintains its peak SNDR over a wide input range, featuring more flexibility. Fabricated in a 65nm CMOS technology, the ADC consumes 46.1μW at 35MS/s from 1V supply voltage, and achieves an SNDR of 51dB and an ENOB of 8.18bits at Nyquist rate, resulting in a figure of merit (FoM) of 4.5fJ/conversion-step. The core circuit only occupies 0.009mm2, which is very compact." @default.
- W1511039581 created "2016-06-24" @default.
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- W1511039581 date "2015-05-01" @default.
- W1511039581 modified "2023-09-27" @default.
- W1511039581 title "A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area" @default.
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- W1511039581 doi "https://doi.org/10.1109/iscas.2015.7169177" @default.
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