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• W1511444804 abstract "In the paper new implementations of double edge-triggered (DET) flip-flops using one latch are presented. In the proposed circuits data are sampled into the latch during a short transparency period for each edge of the clock signal. Three implementations (dynamic, semi-static and static) of the one-latch DET flip-flop are presented and compared with standard two-latch DETs. SPICE simulations of power dissipation as a function of the switching activity of input signal are presented. One-latch DETs have reduced transistor count and lower power dissipation with respect to previously reported DET flip-flops. Power saving is relevant when an array of flip-flops share a single clock driver and for large input signal transition probability." @default.
• W1511444804 created "2016-06-24" @default.
• W1511444804 creator A5050933189 @default.
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• W1511444804 date "2003-01-20" @default.
• W1511444804 modified "2023-09-26" @default.
• W1511444804 title "Power dissipation in one-latch and two-latch double edge triggered flip-flops" @default.
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• W1511444804 doi "https://doi.org/10.1109/icecs.1999.814435" @default.
• W1511444804 hasPublicationYear "2003" @default.
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