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- W1512149211 abstract "The design of control units of modern processors is quite complex due to many speed-up techniques like pipelining and out-of-order execution. The existing approaches to formal verification of processor designs are applicable to very high level descriptions that ignore timing details of control signals. In this paper, we propose an approach for verification of detailed design of processors. Our approach suggests the use of Esterel language which has rich constructs for succinct and modular description of control. The Esterel simulation tool Xes and verification tools Xeve and FcTools can be used effectively to catch minor bugs as well as subtle timing errors. As an illustration, we have developed an Esterel implementation of DLX pipeline control and verified certain crucial properties." @default.
- W1512149211 created "2016-06-24" @default.
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- W1512149211 date "1999-01-01" @default.
- W1512149211 modified "2023-09-23" @default.
- W1512149211 title "Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study" @default.
- W1512149211 cites W2081938726 @default.
- W1512149211 doi "https://doi.org/10.1007/3-540-48683-6_10" @default.
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