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• W1513868814 abstract "This paper presents the design and test results of a 4th and 6th order, 14-bit, 2.2MS/s sigma-delta ADC. The analog modulator and digital decimator sections were implemented in a .35µM CMOS, double poly, triple level metal 3.3v process. The design objectives for these ADCs was to achieve 85dB SNDR with less than 200mW power dissipation." @default.
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• W1513868814 date "1999-01-01" @default.
• W1513868814 modified "2023-09-23" @default.
• W1513868814 title "14&#8211;bit, 2.2MS/s sigma delta ADCs" @default.
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