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- W1514139802 abstract "A new logic-timing simulation algorithm, applicable to cycle-based simulation of acyclic combinational logic blocks or synchronous logic designs, is described and implemented. The algorithm is based on evaluating ordered sequences of events, called event-streams, instead of individual events as in a traditional event-driven simulator. This allows very efficient gate evaluations using states unrolling and look-ahead processing. When processing long event-streams, the performance of our simulator can approach that of a compiled-code simulator without the poor instruction-cache behavior of large compiled-code simulations. In addition, the simulator can perform multi-cycle simulations that result in longer event-streams, which enhances the efficiency of gate evaluations. Experimental results show that our simulator runs about four times faster than the Verilog-XL simulator." @default.
- W1514139802 created "2016-06-24" @default.
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- W1514139802 date "2002-12-24" @default.
- W1514139802 modified "2023-09-25" @default.
- W1514139802 title "Cycle-based timing simulations using event-streams" @default.
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- W1514139802 doi "https://doi.org/10.1109/iccd.1996.563594" @default.
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