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• W1514373262 abstract "The signal-processing functions required to implement echo-cancelling transceivers with 2B1Q line code for ISDN (integrated-services digital network) basic-rate-access digital subscriber loops are discussed. The simplifications that follow from the use of 2B1Q are presented. It is concluded that transceivers that sacrifice an insignificant amount of the excellent performance of 2B1Q can be realized very efficiently. Decision-directed timing recovery, control of the echo tail by high-pass filtering, and simple algorithm modifications to negate the effect of four-level signals on complexity reduce the required digital signal processing largely to the implementation of highly structured algorithms of moderate complexity. Switched-capacitor-based transmitters, dual amplifier differential line driving, and DSM A/D (analog-to-digital) conversion provide analog interface functions capable of giving the necessary performance in 5-V CMOS technology. >" @default.
• W1514373262 created "2016-06-24" @default.
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• W1514373262 date "2003-01-06" @default.
• W1514373262 modified "2023-09-25" @default.
• W1514373262 title "Considerations in the VLSI circuit implementation of 2B1Q transceivers" @default.
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• W1514373262 doi "https://doi.org/10.1109/iscas.1988.15059" @default.
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